Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif

DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs

https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf

@vlsihub

CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.

Links:? https://doi.org/10.1145/3626202.3637575
*?*** https://github.com/kiabuzz/CompressedLUT

#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic

Generate Compilers from Hardware ModelsCompiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

*?*** https://arxiv.org/abs/2305.09580

@vlsihub