Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.

With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.

Links:
? https://ieeexplore.ieee.org/document/9114755
*?*** https://github.com/RC4ML/Shuhai

#memory #ddr #hbm #benchmark
@fpgasic

Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif

DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs

https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf

@vlsihub

CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.

Links:? https://doi.org/10.1145/3626202.3637575
*?*** https://github.com/kiabuzz/CompressedLUT

#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:? https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
*?*** https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic

Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:? http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
*?*** https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic

Generate Compilers from Hardware ModelsCompiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

*?*** https://arxiv.org/abs/2305.09580

@vlsihub

OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:? openvaf.semimod.de/
*?*** github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic

Open-source IC cells as 3D prints. A rough how-to guideThis util can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used.

? https://medium.com/@thorstenknoll/open-source-ic-cells-as-3d-prints-a-rough-how-to-guide-90a8bc8b3b57
*?*** https://github.com/trilomix/GDS3D

@vlsihub