fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

This algorithm is fast, since the sorting itself is done in parallel while the data is being input serially. It is sorted and ready to be read back immediately following the last write transfer.

A 256-length, 8-bit sorter costs approximately 5500 logical elements on an Altera Cyclone IV.

Links:
? https://github.com/Poofjunior/fpga_fast_serial_sort

#algo #sort #sorting
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**FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Motors (PMSM) or Brushless DC Motors (BLDC)

Features*▫️Support 3 channels of PWM + 1 channel of EN
▫️Supports angle sensor and phase current sampling ADC with 12bit resolution
▫️Internally uses 16bit signed integer* for computation

Links? https://github.com/WangXuan95/FPGA-FOC

#verilog #BLDC #PMSM #FOC #motor
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**Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA

Features*▫️Specifically designed for the 256/512/1024 bit wide AXI4-Stream interface
▫️Generic MSI-X compatible interrupt controller.
▫️Supporting PCIe Gen3, Gen4 and Gen5
▫️*Supporting Series 7, UltraScale, Ultrascale+, Versal Prime and Versal Premium FPGAs

Links? https://gitlab.nikhef.nl/franss/wupper/
? https://gitlab.nikhef.nl/franss/wupper/-/blob/master/documentation/wupper.pdf

#PCIE #DMA #Xilinx #FPGA #VHDL
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Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantissa and exponent.

Features▫️Fully parametrizable bit widths for exponent and mantissa
▫️Handles all special cases:
▪️ SNaN/QNaN
▪️ ± infinity
▪️ Denormalized numbers
▪️ Zeroes
▫️Single cycle operation
▫️Supports rounding to nearest (per official specification) or simply chopping bits

Links? https://github.com/V0XNIHILI/parametrizable-floating-point-verilog

#IEEE754 #FP #arithmetic
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NNgen is an open-sourced compiler to synthesize a model-specific hardware accelerator for deep neural networks. NNgen generates a Verilog HDL source code and an IP-core package (IP-XACT) of a DNN accelerator from an input model definition.

Generated hardware is all-inclusive, which includes processing engine, on-chip memory, on-chip network, DMA controller, and control circuits. So the generated hardware does not require any additional controls from an external circuit or the CPU after the processing is started.

Links? https://github.com/NNgen/nngen

#nn #onnx #dl #ml #compiler
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FPnew - New Parametric Floating-Point Unit with Transprecision Capabilities

Operations:
▫️Addition/Subtraction
▫️Multiplication
▫️Fused multiply-add in four flavours (fmadd, fmsub, fnmadd, fnmsub)
▫️Division
▫️Square root
▫️Minimum/Maximum
▫️Comparisons
▫️Sign-Injections (copy, abs, negate, copySign etc.)
▫️Conversions among all supported FP formats
▫️Conversions between FP formats and integers (signed & unsigned) and vice versa
▫️Classification

Links? https://github.com/openhwgroup/cvfpu

#ieee754 #fp #floatingpoint
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FPGA-FFT - a highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Features▫️Data input/output are continuous with no gaps between frames
▫️Support power-of-two sizes
▫️Support fixed point data
▫️Resource usage is on par with Xilinx FFT IP core
▫️Fmax is up to 30% higher for common sizes than Xilinx FFT IP core

Links? https://github.com/owocomm-0/fpga-fft

#fft #dsp #vhdl #xilinx
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Send video/audio over HDMI on an FPGA

SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.

Features▫️ 24-bit color
▫️ Data island packets
▫️ Null packet
▫️ ECC with BCH systematic encoding GF(2^8)
▫️ Audio clock regeneration
▫️ L-PCM audio 2-channel
▫️ Audio InfoFrame
▫️ Video formats 1, 2, 3, 4, 16, 17, 18, 19
▫️ VGA text mode
▫️ IBM 8x16 font
▫️ Double Data Rate I/O (DDRIO)
▫️ Supports up to 3840x2160@30Hz

Links? https://github.com/hdl-util/hdmi
? https://purisa.me/blog/hdmi-released/

#HDMI #video #SV #SystemVerilog
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An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.

Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.

The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.

Links:? https://github.com/LukiLeu/FPGA_ADC
? https://dl.acm.org/doi/10.1145/3431920.3439287

#ADC #VHDL #TDC
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